State of the art systems in package (3-D circuits) utilize a Through Silicon Via (TSV) or through silicon stacking (TSS) to achieve a vertical connection and stack multiple dies in space, resulting in reduced footprint and power consumption, and improving overall performance.
1 Asset 1 Application
Self-organizing network with chip package having multiple interconnection configurations
Inventor Moon J. Kim
Current Assignee KIM MOON J
Original Assignee Moon J. Kim
Priority Date 2010-12-21
In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs.
US 14/925,115 Office Action on-going
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