This portfolio discloses an apparatus, architecture, method, operating system, data network, and application program framework for a hybrid digital system with multiple heterogeneous components. Under this arrangement, different technology cores and functional components are organized such that different technologies can collaborate as a system. The components can be individually upgraded and/or sourced from multiple vendors.

Hybrid multifunction component system with component interface encapsulation including OS packet translator for communication over unified data bus architecture

Inventor  Moon J. Kim
Original Assignee  Kim Moon J
Priority date  2009-06-19

This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of groups of sub-processing components. Under this arrangement, different technology cores and functional components, such as memory, are organized in a way that different technologies can collaborate as a system.

Computationally-Networked Unified Data Bus

Inventor Moon J. Kim
Current Assignee KIM MOON J
Original Assignee Moon J. Kim
Priority date 2010-11-08

Embodiments of the present invention provide a computationally-networked unified data bus for a multi-processing domain architecture. Specifically, in a typical embodiment, a unified data bus is provided. A first data bus adapter (e.g., a node) is coupled to the unified data bus (e.g., a link), and a first processing domain is coupled to the first data bus adapter. In general, the first data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the first processing domain. In addition, a second data bus adapter (e.g., a node) is coupled to the unified data bus and a second processing domain is coupled to the second data bus adapter. Similar to the first data bus adapter, the second data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the second processing domain. Under these embodiments, the first processing domain and the second processing domain can each comprise at least one element selected from a group consisting of: memory input/outputs (I/Os), cache, heterogeneous data buses, and processors. Moreover, the first processing domain and the second processing domain can be selected from a group consisting of a heterogeneous processing domain and a hybrid processing domain.

Memory and process sharing across multiple chipsets via input/output with virtualization

Inventor Moon J. Kim
Current Assignee KIM MOON J
Original Assignee Moon J. Kim

Priority date 2012-04-11

Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

Memory and process sharing via input/output with virtualization
Inventor Moon J. Kim
Original Assignee Moon J. Kim
Priority date 2012-04-11

Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

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