These patents will improve the power consumption (low-power) of the mobile device.

Total 3 Assets

Input/output device power reduction and optimization by enablement or disablement of an external circuit coupled to the input/output device

Inventor: Moon J. Kim
Current Assignee: KIM MOON J
Original Assignee: Moon J. Kim
Priority date: 2011-11-28

Embodiments of the present invention provide a processor design that enables controller and I/O device power reduction and optimization. In a typical embodiment, a processing core is coupled to a set (e.g., three) of I/O blocks. The processing core provides for selective activation and/or deactivation of any of the I/O blocks. Two of the I/O blocks are coupled to individual voltage I/O components as well as individual external circuits. In one embodiment, the individual external circuits are coupled to individual voltage control components.

High capacity electronic switch

Inventor: Moon J. Kim
Current Assignee: KIM MOON J
Original Assignee: Moon J. Kim
Priority date: 2011-07-22

Embodiments of the present invention provide an electronic switch for commodity use. Specifically, embodiments of this invention provide a high capacity intelligent electronic switch for commodity use. A flexible film substrate is used along with a field-effect transistor (FET) to produce a commodity switch. Multiple printed flexible electronics PFE substrates are stacked to and integrated into an electronic switch system. Various methods are used to measure power consumption within the switch. The modular cell design allows for horizontal and vertical scaling.

Leakage and performance graded memory

Inventor: Moon J. Kim
Current Assignee: KIM MOON J
Original Assignee: Moon J. Kim
Priority date: 2012-05-31

Embodiments of the present invention provide a memory configuration on a chip containing multiple memory segments having different memory grades. In a typical embodiment, a single chip will be provided on which the memory segments are positioned. A memory grade may include low performance (low leakage), medium performance (medium leakage), and high performance (high leakage). Each memory segment or group of memory segments may have a separate power supply and/or controller. In one example, memory segments may be stacked in a through-silicon via configuration.

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